! File: 3166C.PROP ! Database: PEPDB ! Date: 18-FEB-1994:20:12:58 coverpage: title_1: NSSC-I S/W PAYLOAD SAFING PATCH proposal_for: ENG pi_fname: GLENN pi_lname: FOLEY pi_inst: CODE 512 pi_country: USA num_pri: 1 ! end of coverpage abstract: line_1: This proposal was developed to install the "software line_2: payload safing" patch to the HST NSSC-I Baseline 3.12a line_3: flight software. This approach requires both realtime line_4: and stored command elements. Stored commands will be used line_5: to perform the actual patching of memory and realtime line_6: actions will activate the sorted command sequences and line_7: monitor the progress of the installation. line_8: Installation requires modification of 3 distinct regions line_9: of memory. The first is a 34 word section to be placed in line_10: in bank 4 (numbering from 0) which contains the data line_11: referenced by the new code. The 2nd is the code which actually line_12: performs the new functionality. It is a 44 word region to be line_13: placed in bank 7. The 3rd area is in the existing NSSC-I code line_14: which processes the SSM PIT. It is a 14 word region in bank 6 line_15: which will link the existing code to the new code. 4 NSSC-I line_16: relative time command sequences (RTCSs) are required for the line_17: installation: one to memory load each of the 3 above regions line_18: and a 4th to return the code to its original config.,disabling line_19: disabling the new ability. These will be referred to as the Data line_20: Patch RTCS, New Code RTCS, Linkage Patch RTCS, and Unpatch RTCS. ! ! end of abstract general_form_proposers: lname: FOLEY fname: GLENN inst: GFSC/CODE 512 country: USA esa: X ! ! end of general_form_proposers block general_form_text: question: 2 section: 1 line_1: The Data Patch RTCS consists of a trivial memory load. It line_2: has the form: line_3: memory load 34 words line_4: The New Code Patch RTCS also contains a memory load, but line_5: its logic is more complex since it must modify a region of line_6: memory that is protected against change by the NSSC-I flight line_7: s/w. Before it can be loaded, the RTCS line_8: must deactivate the error processing performed by the NSSC-I line_9: memory checksum diagnostic and change a constant which delimits line_10: the region of memory that can be memory loaded. This is of the line_11: form: line_12: disable checksum error processing line_13: change code start constant line_14: memory load 44 words line_15: restore code start constant line_16: wait 4mins line_17: enable checksum error processing line_18: The Linkage Patch and the unpatch RTCSs also require deactiva line_19: ting the checksum error processing and changing the code start line_20: constant, but have another level of complexity: both involve line_21: modifying the code of an interrupt handler which executes line_22: every .5 secs and cannot be disabled (SSM PIT processing). ! question: 3 section: 1 line_1: It must be assured that the interrupt does not occur when line_2: the memory load is in progress, thus the elements of the RTCS line_3: which perform the load must be coordinated with the expected line_4: arrival of the SSM PIT. The linkage patch is of the form: line_5: disable checksum error proc. line_6: change code start constant line_7: wait for NOT start of major frame line_8: wait for start of major frame line_9: wait for 40 minor frames plus 175 millisecs line_10: memory load 14 words line_11: restore code start constant line_12: wait 4mins line_13: enable checksum error proc. line_14: The Unpatch RTCS is of the form: line_15: disable checksum error proc. line_16: change code start constant line_17: wait for NOT start of major frame line_18: wait for start of major frame line_19: wait for 40 minor frames plus 175 millisecs line_20: memory load 14 words line_21: memory load 44 words line_22: restore code start constant ! question: 3 section: 2 line_1: wait 4mins line_2: enable checksum error proc. line_3: In the unpatch RTCS the memory load of 14 workds is done to line_4: restore the code in the SSM PIT proc. software used to link line_5: to the new code, to its previous baseline 3.12a config. line_6: The memory load of 44 words will return the area used for line_7: the new code to zero. line_9: The order in which the RTCSs are activated is line_10: critical. However the timing between steps relative to one line_11: another is not: time which elapses between any two steps line_12: may be of arbitrary duration line_13: time critical are in the NSSC-I RTCSs. The QMONDADDS line_14: Table refer to the NSSC-I memory monitor programmable line_15: telemetry capability. This Table may be loaded with line_16: the addresses of up to 20 locations in NSSC-I memory and line_17: the contents of those locations reported in the eng'rng line_18: telemetry every 30secs. ! question: 3 section: 3 line_1: INSTALLATION STEPS: line_3: SETUP line_5: 0. s/w dump NSSC-I memory banks 0-11 decimal (12 banks); line_6: update Ground Master Image after each dump. line_7: 1. initial config: C&DH in normal mode; 4 installation RTCSs line_8: loaded in NSSC-I stored command memory and enabled line_9: 2. condition QMONADDS table slots 17-20 and look at locations line_10: in NSSC-I memory: line_11: slot 17 - SSMPIT (1st word of SSM PIT received line_12: contains safing bits) line_13: slot 18 - QMEMCHEK (indicates whether checksum error line_14: proc. enabled) line_15: slot 19 - QLIMITS (code start constant) line_16: slot 20 - QMEMCKSM (value calc.by checksum proc.) line_18: Data Section line_20: 3. Condition QMONADDS table slots 1-16 to look at 1st 16 words line_21: of data patch area line_22: 4. activate the Data Patch RTCS ! question: 3 section: 4 line_1: 5. verify the first 16 words of the data patch area with line_2: memory monitors; snap page CDHMEMOC line_3: 6. condition QMONADDS table slots 1-16 to look at 2nd 16 words line_4: of Data Patch area line_5: 7. verify 2nd 16 words with memory monitors; snap page CDHMEMOC line_6: 8. condition QMONADDS table slots 1-2 to look at last 2 words line_7: of data patch are line_8: 9. verify last 2 words via memory monitors; snap page CDHMEMOC line_10: New Code Section line_12: 10. activate New Code Patch RTCS line_13: 11. verify new checksum is octal 715250 w/memory monitors line_14: 12. verify New Code Patch complete (MOC page CDH1) line_16: Linkage Section line_18: 13. acitivate Linkage Patch RTCS line_19: 14. verify new checksum is octal 760721 w/memory monitors line_20: 15. verify Linkage Patch complete (MOC page CDH1) ! question: 3 section: 5 line_1: Cleanup Section line_3: 16. s/w dump NSSC-I memory banks 4,6,7 (numbering from 0); line_4: print descrepancy report; verify patched areas; update line_5: Ground Master Image after each bank is dumped. line_7: Procedure to deinstall the patch would be to activate the line_8: Unpatch RTCS. The final checksum octal would be 020402, line_9: the initial NSSC-I baseline 3.12a value. ! question: 5 section: 1 line_1: Estimated Vehicle Resources are given for the sections line_2: of the realtime procedure labelled Setup, Data, New Code line_3: Linkage and Cleanup. Resources are divided into SSA line_4: forward link time, MA engineering return link time, 1M line_5: SA science return link time, and the time required line_6: before proceeding to next section ("think" time). SSA line_7: and 1M SSA science links should be scheduled coincident line_8: with or near the start of the associated MA return links. line_9: The sole use of the SDF is required for the memory dumps in line_10: steps 0-16. All times are in minutes. line_12: STEPS SSA LINK MA ENG RETURN 1M SSA SCI. THINK TIME line_13: 0 25 25 25 0 line_15: 1-2 10 15 0 10 line_16: 3-5 10 15 0 10 line_17: 6-7 10 15 0 10 line_18: 8-9 10 15 0 10 line_19: 10-12 10 15 0 20 line_20: 13-15 10 15 0 20 line_21: CONTINGENCY TIME: 10M FOR SSA, 15M FOR MA ENG. line_22: 16 10 10 10 10 ! question: 5 section: 2 line_1: No other RTCSs with executive ownership can be activated line_2: when the Linkage Patch is active because nesting may line_3: perturb the critical time designed into the sequence. line_4: It is also desirable to have ALL SIs in HOLD MODE during line_5: Linkage Patch activation, to minimize activity in the NSSC-I. line_6: NOTE: though such constraints on the NSSC-I are not required for line_7: activation of the Data Patch or New Code Patch, having the line_8: SI's in hold mode will aid in the potential completion of line_9: their installation ahead of schedule, and the NNSC-I will line_10: already be in the required configuration for the Linkage Patch. line_11: The S/W payload safing patch will be declared operational line_12: during the "think time" of the Linkage section if the line_13: verifications are successful. "Contingency time" is for the line_14: case where a contact is missed or extra time was required to line_15: complete a step. If deemed necessary, the Unpatch RTCS will be line_16: implemented in the next forward link. ! !end of general form text general_form_address: lname: FOLEY fname: GLENN category: PI inst: GFSC/CODE 512 ! ! end of general_form_address records ! No fixed target records found ! No solar system records found ! No generic target records found exposure_logsheet: linenum: 1.000 targname: DARK config: S/C opmode: DATA aperture: NONE num_exp: 1 time_per_exp: 1M fluxnum_1: 1 priority: 1 req_1: CYCLE 0 / 1-2; comment_1: REQUIRED TO INSTALL comment_2: 4 RTCS'S, CONDITION TABLE comment_3: SLOTS 17-20 TO LOOK AT comment_4: SSMPIT, QMEMCHECK, QLIMITS comment_5: AND QMEMCKSM, IN NSSC-1. comment_6: SHOULD BE EXECUTED AS EARLY ! linenum: 2.000 targname: DARK config: S/C opmode: DATA aperture: NONE num_exp: 1 time_per_exp: 20M fluxnum_1: 1 priority: 1 req_1: REQ UPLINK; req_2: RT ANALYSIS; comment_1: REQUIRES ALL SI'S IN HOLD,BUT HSP IN comment_2: SYSON, WFPC IN STANDBY. comment_3: MODE TO ACTIVATE LINKAGE comment_4: PATCH (LP) RTCS. ID'S MSSLN001/ comment_5: EMSSLINK. VERIFY NEW CHECKSUM comment_6: OCTAL=760721 W/MEM. MONITORS ! ! end of exposure logsheet ! No scan data records found